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Testing Semiconductor Memories: Theory and Practice

hardcoverJanuary 1, 1998
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ISBN-13: 9780471925866 ISBN-10: 0471925861
Publisher
John Wiley & Sons Inc
Binding
hardcover
Published
January 1, 1998
Weight
2.5 lbs
Dimensions
24.10×3.20×19.70 cm

About this book

Testing Semiconductor Memories: Theory and Practice by A. J. Van De Goor. hardcover edition. ISBN: 9780471925866.

Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles,is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory.